Intel's Fifth Generation Xeon Processor Debut: Emerald Rapids Benchmark Test

We were fortunate enough to have a live broadcast with some Intel experts the day before the event, discussing some details of the Intel Core Ultra series processors. We suggest you check it out when you have time. In that live broadcast, we exclusively saw some Core Ultra benchmark tests for the first time and subsequently conducted a comprehensive evaluation of laptops based on Core Ultra.

Here, we will discuss the new Intel 5th generation Intel Xeon processor, codenamed Emerald Rapids. The fifth generation Intel Xeon processor is an evolution of Sapphire Rapids, which we evaluated earlier this year and provided many subtle improvements and enhancements to enhance power efficiency and performance.

The 5th generation Xeon scalable processors adopt the same core microarchitecture as the 4th generation brothers based on Sapphire Rapids, manufactured using the same Intel 7 process, and compatible with the same slots and platforms. Therefore, almost all Intel partners can quickly transition to server products with the 5th generation Xeon scalable processors. These new processors have benefited from another year of improvements in Intel's manufacturing process, and have adopted some adjustments to firmware, packaging, and chip design to improve performance and efficiency.

The maximum number of cores for the 4th generation Xeon processor is 60, while the 5th generation Xeon scalable processor has a maximum of 64 cores per CPU. These updated processors are also equipped with an optimized memory controller that is compatible with DDR5 memory and can run at speeds up to 5600MT/s. For IT decision-makers currently considering purchasing new servers, the cache configuration upgraded by Emerald Rapids may be the most interesting. At the top of the stack, some 5th generation Xeon scalable processor models, featuring dual 32 core XCC tiles, will have approximately 3 times LLC (last level cache) and a total of 320MB. Many data center workloads benefit greatly from large caches located near the processor core, so this independent upgrade may be crucial for some Intel customers. The 5th generation Xeon scalable processor is also equipped with a UPI 2.0 link with a speed of up to 20GT/s, and supports Intel's trusted domain extension, as well as a trusted execution environment supported by hardware.

Another update of the 5th generation Xeon scalable processor is support for CXL type 3 memory, using Compute Express Link 1.1. CXL Type 3 devices can expand the main memory of the system through the CXL interface. Of course, the 5th generation Xeon scalable processor also has support for up to 12 channels of local memory (similar to the 4th generation Xeon processor). The combination of 12 channel DDR5 memory and CXL Type 3 additional devices can be used to expand capacity or increase bandwidth to achieve large in memory databases and other big data workloads, or virtual machine expansion.

Like the 4th generation Xeon processors based on Sapphire Rapids, the 5th generation Xeon processors feature multiple tile configurations. The top-level "XCC" processor uses two tile chips (each tile has a maximum of 32 cores, for a total of 64 cores). The 5th generation of "MCC" uses a single-chip design with a maximum of 32 cores (similar to the 4th generation). The "EE LCC" Xeon processor also adopts a single chip design, with a maximum of 20 cores.

Switching from the four tiles of the XCC processor on Sapphire Rapids to the two larger tiles on Emerald Rapids improves cache size and power efficiency. This has also led to some delay improvements. When data travels through tiles, there are performance and latency impacts, which are minimized on Emerald Rapids. The packaging of the largest processor is also relatively simplified and requires less EMI interconnect.

Switching to dual tiles on XCC's 5th generation Xeon scalable processor has changed support for various cluster modes. The fourth generation Xeon processors support SNC (sub NUMA cluster) in SNC4, SNC2, and Quad modes, while the fifth generation Xeon supports SNC2 or Hemi (hemispherical mode). The default configuration for out of the box use is also different. The MCC 5th generation Xeon processor based on a single tile retains support for the same mode and default configuration as the 4th generation Xeon processor.

The use of fewer EMIB interconnects, some adjustments to interconnect frequencies, some manufacturing maturity, and support for newly enhanced active idle modes have resulted in significant improvements in power efficiency for the 5th generation Xeon processors compared to the 4th generation processors. During idle hours, power consumption can be reduced by up to 100W, with additional improvements during low server utilization.

The new optimized power mode provided by the 5th generation Xeon processor can reduce the power consumption of each slot by up to 110W with utilization below 40%. The 5th generation Xeon processors have improved Turbo ratios for five different Turbo levels, ultimately reducing frequency penalties when using AVX512 or AMX instructions.

The lower power consumption, combined with increased Turbo frequency, more cache, and support for faster memory, significantly improves the performance per watt of the 5th generation Xeon processors.

We should also quickly mention some updates to the Xeon D series. The new Xeon D-1800 and Xeon D-2800 series processors are compatible with existing platforms. 12 new models will be launched, with a maximum of 22 cores per CPU. For the low-power portion of network/edge applications, a higher number of cores will be provided. The number of cores in the 70W model has increased from 4 to 8, almost doubling the computing resources of these chips. These chips also add support for Intel Speed Select Technology - Turbo Frequency (Intel SST-TF), which provides the ability to prioritize Turbo frequencies to specific cores. The Xeon D-1800 series also receives support for dual 100Gb Ethernet connections.

The Xeon E-2400 series processors have also undergone some updates. The Xeon D-2400 processor will have up to 8 Raptor Cove cores, with a maximum frequency exceeding 5.5GHz. They also switched to a new slot and adopted DDR5 memory, supporting speeds up to 4800MT/s. Some changes have been made to the PCIe channel configuration (PCIe 3 and PCIe 4), the number of DMI links, and the maximum number of supported USB 3.2 Gen 2.2 ports.

All changes to the 5th generation Xeon processor based on Emerald Rapids will result in improved performance or efficiency, or improvements in workload, depending on the specific situation. Therefore, for customers who are still using the old platform, these processors represent an important upgrade.

From 4th to 5th generations to Celeron processors, Xeon processors are equipped with a series of accelerators to improve performance for specific workloads, far exceeding the capabilities of the CPU core itself. The types of accelerators include:

Intel Advanced Matrix Extension (Intel AMX)

Intel Data Flow Accelerator (Intel DSA)

Intel Memory Analysis Accelerator (Intel IAA)

Intel Dynamic Load Balancer (Intel DLB)

Intel Advanced Vector Extension (Intel AVX) for vRAN

Intel Advanced Vector Extension 512 (Intel AVX-512)

Intel QuickAssist technology (Intel QAT)

Intel encryption acceleration

Like fourth generation silicon wafers, Intel provides on-demand services, allowing customers to expand the accelerator capabilities of their processors as needed. Intel believes that the flexibility of on-demand services adds value to customers as they do not need to pay additional fees for accelerators that may not be used, and can add features based on the availability of accelerators for software utilization in the future. However, the opposite of this viewpoint is that customers may have powerful silicon wafers in a dormant state in the system.

Overall, Intel has released over 30 5th generation Xeon SKUs, a significant decrease compared to the previous generation. The available accelerators in a given type number depend on the predetermined segment of the chip and its position in the stack.